Our main goals are to develop highly efficient integrated circuits which will allow to perform a large part of the artificial intelligence (AI) workload "at the edge," i.e., on the device, locally, and without the need for cloud access.
Chips for edge AI contain custom-designed (co-)processors optimized for AI tasks and are integrated into edge devices. These chips are also known as AI accelerators or neural processing units (NPUs). Such specialized chips are designed to efficiently run AI algorithms, such as deep learning models, using low power and small area, making them suitable for use in a wide range of edge devices, from cameras to industrial IoT systems and medical devices.
In the realm of IoT, edge AI empowers devices to process data locally, enabling quicker responses and reduced data transfer, thus enhancing overall system efficiency and responsiveness. Likewise in the healthcare sector, edge AI plays a pivotal role by enabling real-time diagnostics, personalized treatments, and closed-loop interventions through localized AI processing.
We hope to fortify the innovation and creation of Switzerland within Europe's technological leadership in this edge AI domain. This highly dynamic field of research is of great strategic importance internationally and Switzerland can enhance through this WP many collaborations already happening within European research and industrial partners in order to secure and further develop its position in this domain.
Related Publications
| A Reconfigurable High Dynamic Range Delta-Sigma Front End with Event-Based Decimation for Bandwidth-Efficient Implantable Neural Interfaces | |||||
| Martinez, Natalia; Sapriza, Juan; Schiavone, Pasquale Davide; Bashford, Luke; Jackson, Andrew; Ansaloni, Giovanni; Constandinou, Timothy; Atienza, David | |||||
| 2025-05-28 | 2025 IEEE International Symposium on Circuits and Systems |  | |||
| Keep All in Memory with Maxwell: a Near-SRAM Computing Architecture for Edge AI Applications | |||||
| Eggermann, Grégoire Axel; Ansaloni, Giovanni; Atienza Alonso, David | |||||
| 2025-04-25 | International Symposium on Quality Electronic Design | |  | ||
| BiomedBench: A benchmark suite of TinyML biomedical applications for low-power wearables | |||||
| Samakovlis, Dimitrios; Albini, Stefano; Rodríguez Álvarez, Rubén; Constantinescu, Denisa-Andreea; Schiavone, Pasquale Davide; Peon Quiros, Miguel; Atienza Alonso, David | |||||
| 2024-10-27 | IEEE Design & Test | |  |  | |
| Bank on Compute-near-Memory: Design Space Exploration of Processing-near-Bank Architectures | |||||
| Medina Morillas, Rafael; Chamazcoti, Saeideh Alinezhad; Zapater Sancho, Marina; Ansaloni, Giovanni; Evenblij, Timon; Levisse, Alexandre Sébastien Julien; Biswas, Dwaipayan; Catthoor, Francky; Atienza Alonso, David | |||||
| 2024-10 | International Conference on Hardware/Software Codesign and System Synthesis (CODES 2024) |  | | | |
| An Evaluation Framework for Dynamic Thermal Management Strategies in 3D MultiProcessor System-on-Chip Co-Design | |||||
| Huang, Darong; Costero Valero, Luis Maria; Atienza Alonso, David | |||||
| 2024-09-09 | IEEE Transactions on Parallel and Distributed Systems | | |||