Can we automate integrated circuit design?

Jason Cong, Director of the Center for Domain-Specific Computing (CDSC) of UCLA, has been invited to EPFL by the IC Faculty.

As we are near the end of Moore’s Law scaling, there is a great need to design various kinds of customized accelerators for much higher performance and energy efficiency. But integrated circuit (IC) designs remain a black art to many. Given the success of deep learning in many domains in recent years, a natural question is if it is possible to fully automate IC designs. In this talk, we present our latest research on this topic. By coupling high-level synthesis with a set of deep learning techniques, such as graph-based neural networks and meta learning, as well as microarchitecture guided optimization for regular structures, such as systolic arrays and stencil computation, we show that it is possible to automate IC designs so that most software programmers can design their own customized ICs for a wide range of applications.

Jason Cong is the Volgenau Chair for Engineering Excellence Professor at the UCLA Computer Science Department (and a former department chair), with joint appointment from the Electrical and Computer Engineering Department. He is the director of Center for Domain-Specific Computing (CDSC) and the director of VLSI Architecture, Synthesis, and Technology (VAST) Laboratory. Dr. Cong’s research interests include novel architectures and compilation for customizable computing, synthesis of VLSI circuits and systems, and quantum computing.

He has over 500 publications in these areas, including 16 best paper awards, and 4 papers in the FPGA and Reconfigurable Computing Hall of Fame. He and his former students co-founded AutoESL, which developed the most widely used high-level synthesis tool for FPGAs (renamed to Vivado HLS after Xilinx’s acquisition). He was elected to an IEEE Fellow in 2000, ACM Fellow in 2008, the National Academy of Engineering in 2017, and the National Academy of Inventors in 2020. He is the recipient of the 2022 IEEE Robert Noyce Medal for fundamental contributions to electronic design automation and FPGA design methods.