• Prof. Prashant Nair: Scaling the Memory Wall

    BC420 - Computing Building of EPFL EPFL, Ecublens, Switzerland

    Towards 3D-DRAM-based Accelerators for Efficient Generative Inference Generative AI now underpins search, digital assistants, and media applications, making inference cost a first-order design constraint. Unlike traditional compute-bound workloads, large language and speech models are typically limited by memory bandwidth and capacity rather than raw arithmetic throughput. Thus, their inference cost […]

  • Prof. Luca Carloni of Columbia: Agile and Collaborative System-on-Chip Design with Open-Source Hardware Platforms

    BC420 - Computing Building of EPFL EPFL, Ecublens, Switzerland

    Open-source hardware can play a unique role for the semiconductor industry in the age of sustainable AI. It can enable design reuse, foster collaboration, and support workforce development. ESP (Embedded Scalable Platforms) is an open-source research platform for system-on-chip (SoC) design that combines a modular architecture with an agile design […]

  • DATE 26: Energy and Material Efficiency in Cloud-Edge continuum

    Verona Palazzo della Gran Guardia, Italy

    We are participating in the DATE 26 conference, as part of the organizing committee, in beautiful Verona. We will be contributing a keynote presentation and a workshop. The details of the workshop are below: Energy and Material Efficiency in Cloud-Edge continuum  

  • SwissChips Annual Event

    SwissTech Convention Center Rue Louis Favre 2, Ecublens, EPFL

    Join us on Thursday, June 4, 2026, at the SwissTech Convention Center (STCC) at EPFL in Lausanne for a day bringing together researchers, partners, and members of the Swiss semiconductor community to exchange ideas and discuss the latest developments in chip design and microelectronics in Switzerland. The program will feature […]