Lana Josipović, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne (all from EPFL, Processor Architecture Lab), and Jordi Cortadella (from Universitat Politècnica de Catalunya, Barcelona, Spain) are winners of the Best Paper Award at the 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA ’20), which concluded on February 25 at Seaside, California.

Their paper ‘Buffer Placement and Sizing for High-Performance Dataflow Circuits’ addresses a fundamental problem in dynamically-scheduled high-level synthesis (HLS): how to strategically place buffers into dataflow circuits obtained out of high-level code to optimize their performance. The paper tackles two aspects that are necessary to achieve high-performance circuits: constraining the critical path and maximizing throughput. Lana and colleagues discuss the difficulties of performing such optimizations in the context of dataflow designs and present a performance optimization model based on marked graph theory. Their mixed-integer linear programming (MILP) model successfully achieved maximum design parallelism at the desired clock frequency and with minimal resource cost. Additionally, the authors propose a computationally-efficient strategy to decompose the problem that achieves near-optimal results. The optimizations presented in this paper are crucial to make dynamic scheduling truly competitive with existing HLS techniques.

The annual ACM/SIGDA International Symposium is the premier conference for presentation of advances in all areas related to FPGA technology, such as FPGA architecture, circuit design, high-level abstractions and tools, and design studies. This year’s Best Paper Award was selected from a total of 149 submissions, out of which 25% of the reviewed papers were finally shortlisted for presentation at the conference.

Lana is a Doctoral Assistant at the School of Computer and Communication Sciences and a winner of Google’s PhD Fellowship award in 2018 for outstanding research in the systems and networking domain.

With several publications to her credit, she works on bridging the gap between software and hardware to build efficient circuits for FPGAs.

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