Keynote – Subhasish Mitra: The Future of Datacenter Compute Chips

Prof. Subhasish Mitra

William E. Ayer Professor of Electrical Engineering and Professor of Computer Science at Stanford University

The computation demands of 21st-century abundant-data workloads – such as AI/Machine Learning – far exceed the capabilities of today’s systems. To meet future datacenter needs, we must overcome three fundamental barriers:

• Memory wall: Systems spend excessive time and energy shuttling data between compute and memory, a bottleneck worsened by the slowdown of 2D miniaturization.
• Thermal wall: As energy efficiency benefits of traditional silicon CMOS diminish, heat dissipation becomes a critical challenge for high-power chips.
• Reliability wall: Silent data corruption caused by defective chips increasingly threatens system integrity, demanding urgent solutions.

To break through these walls, we need transformative NanoSystems. We design new chip architectures unlocked by ultra-dense 3D integration of high-speed, low-energy logic, heterogeneous memories, and embedded thermal solutions – the N3XT 3D approach. Multiple N3XT 3D chiplets are integrated through a continuum of chip stacking, interposer, and wafer-level techniques – the N3XT 3D MOSAIC. To scale with growing problem sizes, new Illusion systems orchestrate workloads across N3XT 3D MOSAIC, creating an illusion of a “Dream Chip” – where memory and compute appear co-located, delivering near-ideal energy efficiency and throughput.

Several hardware prototypes, fabricated in industrial facilities, demonstrate the effectiveness of our approach. We target 1,000X improvements in system-level Energy-Delay-Product for abundant-data workloads. We also present new methods for cost-effective tolerance of hardware failures – to overcome the reliability wall and ensure robust system operation.

Subhasish Mitra holds the William E. Ayer Endowed Chair Professorship in the Departments of Electrical Engineering and Computer Science at Stanford University. He directs the Stanford Robust Systems Group, serves on the leadership team of the Microelectronics Commons AI Hardware Hub funded by the US CHIPS and Science Act, leads the Computation Focus Area of the Stanford SystemX Alliance, and is the Associate Chair (Faculty Affairs) of Computer Science.

His research ranges across Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences. Results from his research group have influenced almost every contemporary electronic system and have inspired significant government and research initiatives in multiple countries. He has held several international academic appointments — the Carnot Chair of Excellence in NanoSystems at CEA-LETI in France, Invited Professor at EPFL in Switzerland, and Visiting Professor at the University of Tokyo in Japan.

Prof. Mitra has also consulted for major technology companies including AMD (XIlinx), Cisco, Google, Intel, Merck (EMD Electronics), and Samsung.In the field of Robust Computing, he has created many key approaches for circuit failure prediction, CASP on-line diagnostics, QED system validation, soft error resilience, and X-Compact test compression. Their adoption by industry is growing rapidly, in markets ranging from cloud computing to automotive systems, under various names (Silicon Lifecycle Management, Predictive Health Monitoring, In-System Test Architecture, In-field Scan, In-fleet Scan). His X-Compact approach has proven essential to cost-effective manufacturing and high-quality testing of almost all 21st century systems. X-Compact and its derivatives enabled billions of dollars of cost savings across the industry.