Seaside in Monterey County, California, will host the 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) between February 23 and 25 this year. Recognized as the premier conference for advances in FPGA technology, the symposium draws research papers, tutorial papers on emerging applications and methodologies, and panel discussion proposals. Among the papers being presented at FPGA 2020 are several original submissions and a tutorial paper by computer scientists at EPFL, which comprise a very good representation at the prestigious global event.

The papers by EPFL researchers at FPGA 2020 cover some of the core areas of interest related to FPGA technology. Mirjana Stojilović has led an exceptional all women-authors team  (Seyedeh Sharareh Mirzargar and guest PhD student Zeinab Seifoori) to present an extension to PathFinder FPGA routing algorithm, which enables it to deliver FPGA designs free from risks of crosstalk side-channel attacks. Such attacks represent a serious threat for large designs assembled from various IPs, but Mirjana and colleagues have designed several strategies to show that crosstalk-attack-aware router ensures that no information leaks at a very small penalty.

In her second paper accepted for FPGA 2020, Mirjana and coauthors Ognjen Glamocanin, Louis Coulon, and Francesco Regazzoni (ALaRI, Lugano) address another security concern for FPGAs: side-channel attacks and evaluation of a system’s resistance to such attacks. They present a design and an FPGA implementation of a built-in test, which allows the FPGA to measure its own internal power-supply voltage and compute the t-test statistic in real time.

Mirjana, Sharareh and Andrea Guerrieri present a poster on how to accurately locate malicious power wasting activities by introducing voltage sensors into the FPGA circuits before deployment on the cloud. This voltage monitoring system and a novel sensor measurement metric take advantage of the unused logic and routing resources of the FPGA to pinpoint all malicious power wasting activities.

Moving from security and efficiency to performance, a group of EPFL researchers (Lana Josipović, Andrea Guerrieri and Shabnam Sheikhha, a Summer@EPFL intern), led by Paolo Ienne, team up with Jordi Cortadella (Universitat Politècnica de Catalunya, Spain) to show how to strategically place buffers into dataflow circuits to optimize their performance.

Considering the importance of scheduling in high-level synthesis, Lana Josipović, Paolo Ienne and coauthors Jianyi Cheng, George A. Constantinides and John Wickerson (Imperial College London) propose an approach that combines both dynamic and static scheduling to use the best of both approaches and obtain a high performance benefits.

Staying with performance improvement, Stefan Nikolić and Paolo Ienne team up with Grace Zgheib (Intel Corporation) to show the usefulness of enhancing FPGA architectures with direct connections between Look-Up Tables (LUTs). They present an algorithm that can automatically search the most interesting patterns of such direct connections.

FPGA 2020 will also see Lana Josipović, Andrea Guerrieri, and Paolo Ienne come together once again for the Invited Tutorial on “Dynamatic: From C/C++ to Dynamically Scheduled Circuits.” The tutorial demonstrates Dynamatic, an open-source HLS framework developed at EPFL, which generates synchronous dataflow circuits out of C/C++ code. By describing some of the applications of Dynamatic, the tutorial will enable others to use the tool and allow them to contribute to its enhancement.

Last but not least, a collaborative effort by James Larus, Endri Bezati, and Seyedmahyar Emami will see an important poster presentation at FPGA 2020. Their work presents a single programming model and the StreamBlocks framework for hardware-software stream programs on heterogeneous platforms. The main advantage of their programming model is the direct support for hardware-software systems, in which an FPGA functions as a coprocessor to a CPU.

EPFL has always had a strong representation in previous editions of the FPGA conference. This year, however, the collection of papers, tutorial, and posters—comprising almost 20% of the conference program—significantly augments EPFL’s contribution to novel research and advancements in FPGA architecture, security and design.