Team
 | Ansaloni Giovanni |
 | Atienza Alonso David |
 | Klein Joshua Alexander Harrison |
 | Levisse Alexandre Sébastien Julien |
 | Rios Marco Antonio |
 | Yu Pengbo |
Sources of Funding
| WiPLASH H2020 |  |
| Compusapien |  |
With the spead of data analytics on the edge, more and more complex machine learning algorithms are being deployed on low power devices. As these algorithms require huge amount of almost non-changing data, the use of non-volatile memories seems to be a solution to the huge leakage induced by SRAM memories.
In this reseach line, we propose to explore the integration of emerging memory technologies in computing architecture and how its affect applications running on such platforms.
Videos
Related Publications
| ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning | ||||||
| Klein, Joshua Alexander Harrison; Boybat, Irem; Qureshi, Yasir Mahmood; Dazzi, Martino; Levisse, Alexandre Sébastien Julien; Ansaloni, Giovanni; Zapater Sancho, Marina; Sebastian, Abu; Atienza Alonso, David | ||||||
| 2022-12-09 | IEEE Transactions on Computers (TC) | | | |||
| Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing | ||||||
| Rios, Marco Antonio; Ponzina, Flavio; Ansaloni, Giovanni; Levisse, Alexandre Sébastien Julien; Atienza Alonso, David | ||||||
| 2021-02-01 | DATE 2021 Design, Automation and Test in Europe Conference, Virtual Conference and Exhibition, February 1-5, 2021 |  | | | ||
| Write Termination circuits for RRAM : A Holistic Approach From Technology to Application Considerations | ||||||
| Levisse, Alexandre Sébastien Julien; Bocquet, Marc; Rios, Marco Antonio; Alayan, Mouhamad; Moreau, Mathieu; Molas, Gabriel; Vianello, Elisa; Atienza Alonso, David; Portal, Jean-Michel | ||||||
| 2020-06-05 | IEEE Access | | | |||
| RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures | ||||||
| Shikhar Tuli, Marco Antonio Rios, Alexandre Sébastien Julien Levisse, David Atienza Alonso | ||||||
| 2020-01-13 | IEEE/ACM Asia and South Pacific Design Automation Conference ASP-DAC 2020 | | ||||
| A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance | ||||||
| Simon, William Andrew; Levisse, Alexandre Sébastien Julien; Zapater Sancho, Marina; Atienza Alonso, David | ||||||
| 2020 | 28th IFIP/IEEE International Conference on Very Large Scale Integration | |  | | | |
| Functionality Enhanced Memories for Edge-AI Embedded Systems | ||||||
| Alexandre Levisse; Marco Rios, William Simon; P-E. Gaillardon, David Atienza | ||||||
| 2019-11-25 | Non-Volatile Memory Technology Symposium 2019 | | ||||
| RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM | ||||||
| Deepak M. Mathew, André Lucas Chinazzo, Christian Weis, Matthias Jung, Bastien Giraud, Pascal Vivet, Alexandre Levisse, Norbert Wehn | ||||||
| 2019-08-08 | International Conference on Embedded Computer Systems SAMOS 2019: Embedded Computer Systems: Architectures, Modeling, and Simulation | | ||||
| Switching event detection and self-termination programming circuit for energy efficient ReRAM memory arrays | ||||||
| Mouhamad Alayan, Eloi Muhr, Alexandre Levisse, Marc Bocquet, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, Jean Michel Portal | ||||||
| 2019-04-02 | IEEE Transactions on Circuits and Systems II 2019 | | ||||
| Resistive Switching Memory Architecture Based on Polarity Controllable Selectors | ||||||
| Alexandre Levisse, Pierre-Emmanuel Gaillardon, Bastien Giraud, Ian O'Connor, Jean-Philippe Noel, Mathieu Moreau, Jean-Michel Portal | ||||||
| 2018-12-21 | IEEE Transactions on Nanotechnology 2018 | | ||||