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X-WR-CALDESC:Events for EcoCloud
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DTSTART;TZID=Europe/Paris:20260401T121500
DTEND;TZID=Europe/Paris:20260401T131500
DTSTAMP:20260609T181149
CREATED:20260319T150743Z
LAST-MODIFIED:20260319T150827Z
UID:11826-1775045700-1775049300@ecocloud.epfl.ch
SUMMARY:Prof. Prashant Nair: Scaling the Memory Wall
DESCRIPTION:Towards 3D-DRAM-based Accelerators for Efficient Generative Inference\nGenerative AI now underpins search\, digital assistants\, and media applications\, making inference cost a first-order design constraint. Unlike traditional compute-bound workloads\, large language and speech models are typically limited by memory bandwidth and capacity rather than raw arithmetic throughput. Thus\, their inference cost is driven as much by data movement as by compute\, and therefore hinges on the memory system’s design. This concern is especially acute during autoregressive decoding\, which must repeatedly stream model weights and key–value (KV) caches at high bandwidths and low latencies while also providing enough capacity to support long context windows and several concurrent users. To make matters worse\, these demands are accelerating with state-of-the-art models now exceeding hundreds of billions of parameters\, context windows expanding from 4K to 128K tokens and beyond\, and mixture-of-experts designs introducing additional irregularity in memory access patterns. Thus\, today’s memory technologies force difficult trade-offs. SRAM can deliver extremely high bandwidth\, but at prohibitive area and capacity limits. HBM offers higher capacity\, but remains constrained by achievable bandwidth and I/O power. Closing this gap will require a fundamental rethinking of how memory is integrated with accelerator logic. \nIn this talk\, I will introduce our upcoming memory-centric accelerator\, which vertically integrates logic with 3D-stacked DRAM to deliver SRAM-level bandwidth and HBM-class capacity while substantially reducing energy consumption. I will describe the architectural challenges addressed by workload-aware channel mapping\, optimized power management\, topology-preserving redundancy\, and thermal-aware reliability mechanisms\, enabling the practical deployment of 3D-DRAM. Evaluations using models such as Llama-3.1\, DeepSeek-V3\, Canary\, and Whisper show that our accelerator achieves significantly higher throughput and responsiveness compared to HBM-based alternatives. I will conclude by examining the broader implications for computer architecture\, particularly how advanced logic-memory integration through hybrid bonding and multi-high stacking can reshape inference cost structures and enable the next generation of trillion-parameter models. \nBiography: Prashant J. Nair is the lead architect of the 3D-memory architecture at d-Matrix for their upcoming accelerators. He is also an Associate Professor at the University of British Columbia (UBC)\, where he leads the Systems and Architectures (STAR) Lab\, and an Affiliate Fellow of the Quantum Algorithms Institute. His research focuses on memory architectures and systems. Dr. Nair’s recognitions include the 2024 TCCA Young Architect Award (the highest early-career honor in computer architecture)\, the 2025 DSN Test of Time Award\, the HPCA 2023 Best Paper Award\, a MICRO 2024 Best Paper nomination\, and the HPCA 2025 Distinguished Artifact Award. Over the past decade\, he has published more than 40 papers in top-tier venues. Prior to his promotion to Associate Professor\, as an Assistant Professor\, he was inducted into all three halls of fame of computer architecture: ISCA\, MICRO\, and HPCA. \nWebsite: https://prashantnair.bitbucket.io/ \nMost Recent Co-Lead Project: https://gimletlabs.ai/blog/low-latency-spec-decode-corsair 
URL:https://ecocloud.epfl.ch/event/prof-prashant-nair-scaling-the-memory-wall/
LOCATION:BC420 – Computing Building of EPFL\, EPFL\, Ecublens\, Switzerland
CATEGORIES:EcoCloud Official Event
ATTACH;FMTTYPE=image/jpeg:https://ecocloud.epfl.ch/wp-content/uploads/2026/03/prashant.jpg
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DTSTART;TZID=Europe/Paris:20260417T111500
DTEND;TZID=Europe/Paris:20260417T111500
DTSTAMP:20260609T181149
CREATED:20260413T052406Z
LAST-MODIFIED:20260413T083025Z
UID:11845-1776424500-1776424500@ecocloud.epfl.ch
SUMMARY:Prof. Luca Carloni of Columbia: Agile and Collaborative System-on-Chip Design with Open-Source Hardware Platforms
DESCRIPTION:Open-source hardware can play a unique role for the semiconductor industry in the age of sustainable AI. It can enable design reuse\, foster collaboration\, and support workforce development. ESP (Embedded Scalable Platforms) is an open-source research platform for system-on-chip (SoC) design that combines a modular architecture with an agile design methodology. The ESP architecture simplifies the design and prototyping of heterogeneous chips with multiple RISC-V processor cores and dozens of loosely coupled accelerators\, all interconnected by a scalable network-on-chip. The ESP methodology promotes system-level design while accommodating different specification languages and design flows. \nESP’s capabilities have enabled a small team\, primarily composed of graduate students\, to realize two SoCs of increasing complexity\, each within a few months. Conceived as a heterogeneous system integration platform and refined through years of teaching at Columbia University\, ESP is well suited to advance collaborative engineering across the open-source hardware community. \nThis talk will be followed by a standing lunch next to BC420 from 12:15 to 13:30. \nBio: \nLuca Carloni is professor and chair of Computer Science at Columbia University in the City of New York. He holds a Laurea Degree Summa cum Laude in Electronics Engineering from the University of Bologna\, Italy\, and an MS in Engineering and a PhD in Electrical Engineering and Computer Sciences\, both from the University of California\, Berkeley. His research interests include heterogeneous computing\, system-on-chip platforms\, embedded systems\, and open-source hardware. He co-authored over two hundred refereed papers. \nLuca received the NSF CAREER Award\, the Alfred P. Sloan Research Fellowship\, and the ONR Young Investigator Award. In 2025\, he received the IEEE/ACM A. Richard Newton Technical Impact Award in Electronic Design Automation for the paper “Latency-Insensitive Protocols” and the Columbia Engineering School (SEAS) Alumni Distinguished Faculty Teaching Award. He is an ACM Fellow and an IEEE Fellow.
URL:https://ecocloud.epfl.ch/event/dr-luca-carloni-of-berkeley-agile-and-collaborative-system-on-chip-design-with-open-source-hardware-platforms/
LOCATION:BC420 – Computing Building of EPFL\, EPFL\, Ecublens\, Switzerland
CATEGORIES:EcoCloud Official Event
ATTACH;FMTTYPE=image/jpeg:https://ecocloud.epfl.ch/wp-content/uploads/2026/04/carloni.jpg
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BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20260422T140000
DTEND;TZID=Europe/Paris:20260422T160000
DTSTAMP:20260609T181149
CREATED:20260414T082600Z
LAST-MODIFIED:20260414T084729Z
UID:11867-1776866400-1776873600@ecocloud.epfl.ch
SUMMARY:DATE 26: Energy and Material Efficiency in Cloud-Edge continuum
DESCRIPTION:We are participating in the DATE 26 conference\, as part of the organizing committee\, in beautiful Verona. \nWe will be contributing a keynote presentation and a workshop. The details of the workshop are below: \nEnergy and Material Efficiency in Cloud-Edge continuum \n 
URL:https://ecocloud.epfl.ch/event/date-26-energy-and-material-efficiency-in-cloud-edge-continuum/
LOCATION:Verona\, Palazzo della Gran Guardia\, Italy
ATTACH;FMTTYPE=image/jpeg:https://ecocloud.epfl.ch/wp-content/uploads/2026/04/verona.jpg
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