BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//EcoCloud - ECPv6.15.20//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://ecocloud.epfl.ch
X-WR-CALDESC:Events for EcoCloud
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:Europe/Paris
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20260329T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20261025T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20250916T151500
DTEND;TZID=Europe/Paris:20250916T164500
DTSTAMP:20260424T104303
CREATED:20250910T135503Z
LAST-MODIFIED:20250910T140058Z
UID:11464-1758035700-1758041100@ecocloud.epfl.ch
SUMMARY:High-Level Synthesis for Accelerator Design: Current Trends and Emerging Directions
DESCRIPTION:Hardware specialization is increasingly essential to meet the performance and energy demands of modern applications. High-level synthesis (HLS) has emerged as a key enabling technology\, allowing designers to rapidly generate specialized accelerators while exploring complex trade-offs between computation\, communication\, and memory. Significant challenges remain\, however\, including the need to orchestrate efficient data movement across memory hierarchies\, optimize communication architectures\, and protect both data and intellectual property in accelerator design. \nThis talk will discuss how compiler optimizations\, HLS\, and hardware design techniques can be combined to address these challenges. I will first discuss current trends\, including the growing integration of HLS into heterogeneous system design\, advances in communication and memory optimization\, and the increasing role of hardware-level security. I will then highlight emerging directions\, including the use of large language models to support hardware design automation and the integration of HLS into fully open-source EDA tool flows. \nProf. Christian Pilato\nChristian Pilato is an Associate Professor at Politecnico di Milano. He received his Ph.D. in Information Technology from Politecnico di Milano in 2011. He has been a Postdoctoral Researcher at Columbia University and the University of Lugano\, and a Visiting Researcher at New York University\, TU Delft\, and Chalmers University of Technology. \nRead on… \n 
URL:https://ecocloud.epfl.ch/event/high-level-synthesis-for-accelerator-design-current-trends-and-emerging-directions/
LOCATION:ELA2\, EPFL
CATEGORIES:EcoCloud Official Event
ATTACH;FMTTYPE=image/jpeg:https://ecocloud.epfl.ch/wp-content/uploads/2025/09/milan.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Paris:20250925T111500
DTEND;TZID=Europe/Paris:20250925T120000
DTSTAMP:20260424T104303
CREATED:20250915T123146Z
LAST-MODIFIED:20250915T153037Z
UID:11474-1758798900-1758801600@ecocloud.epfl.ch
SUMMARY:The Battle of the Interconnects: Scale-up vs. Scale-out
DESCRIPTION:Dr. Javier Picorel of Huawei \nIn 2020 Dr. Picorel gave a talk at the EcoCloud Annual Event on Edge Computing at Huawei. Now he returns with a fascinating presentation about the battle of the interconnects. \nAs traditional scale-up interconnects like NVIDIA’s NVLink and CXL extend beyond single nodes to span racks and clusters\, and new scale-out networks such as UALink and Broadcom’s SUE emerge for low-latency scenarios\, a competitive shift is underway in computer system design. Meanwhile\, the slowdown of technology scaling is prompting exploration of extreme-scale integration\, with innovations like Cerebras’ Wafer-Scale Engine and Tesla’s Dojo poised to further disrupt interconnect architectures. In this evolving landscape\, the key question remains: which interconnect paradigm will define the future of computing? \nJavier Picorel leads the Future Computer Fabrics team at Huawei’s Zurich Research Center\, where he is driving the development of next-generation decomposable-native infrastructure. His team focuses on the tighter integration of applications\, parallel programming models\, networking\, and compute to enable highly modular and elastic computing architectures. Javier’s research spans a broad range of topics in computer architecture\, computer systems\, computer networks\, and hardware-software co-design. He earned his Ph.D. in Computer Science from EPFL in 2017 and was honored with the Huawei Individual Gold Medal in 2021. In 2022\, his work was prominently featured at Huawei Connect\, the company’s flagship annual technology event. \n12:00 to 14:00pm Standing lunch sponsored by Huawei\, next to room BC420
URL:https://ecocloud.epfl.ch/event/the-battle-of-the-interconnects-scale-up-vs-scale-out/
LOCATION:BC420 – Computing Building of EPFL\, EPFL\, Ecublens\, Switzerland
CATEGORIES:EcoCloud Official Event
ATTACH;FMTTYPE=image/jpeg:https://ecocloud.epfl.ch/wp-content/uploads/2025/09/huaweiCH.jpg
END:VEVENT
END:VCALENDAR